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MCP1725
500 mA, Low Voltage, Low Quiescent Current LDO Regulator
Features
* * * * * * * * * * * * * * 500 mA Output Current Capability Input Operating Voltage Range: 2.3V to 6.0V Adjustable Output Voltage Range: 0.8V to 5.0V Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V Other Fixed Output Voltage Options Available Upon Request Low Dropout Voltage: 210 mV Typical at 500 mA Typical Output Voltage Tolerance: 0.5% Stable with 1.0 F Ceramic Output Capacitor Fast response to Load Transients Low Supply Current: 120 A (typ) Low Shutdown Supply Current: 0.1 A (typ) Adjustable Delay on Power Good Output Short Circuit Current Limiting and Overtemperature Protection 2x3 DFN-8 and SOIC-8 Package Options
Description
The MCP1725 is a 500 mA Low Dropout (LDO) linear regulator that provides high current and low output voltages in a very small package. The MCP1725 comes in a fixed (or adjustable) output voltage version, with an output voltage range of 0.8V to 5.0V. The 500 mA output current capability, combined with the low output voltage capability, make the MCP1725 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1725 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 F of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1725 is typically less than 120 A over the entire input voltage range, making it attractive for portable computing applications that demand high output current. When shut down, the quiescent current is reduced to less than 0.1 A. The scaled-down output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). An external capacitor can be used on the CDELAY pin to adjust the delay from 200 s to 300 ms. The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions.
Applications
* * * * * * * High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers Video Graphics Adapters 2.5V to 1.XV Regulators
Package Types
Adjustable (SOIC-8)
VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 ADJ 6 CDELAY 5 PWRGD
Fixed (SOIC-8)
VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 Sense 6 CDELAY 5 PWRGD
Adjustable (2x3 DFN)
VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT ADJ CDELAY PWRGD
Fixed (2x3 DFN)
VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT Sense CDELAY PWRGD
Note:
DFN tab is at ground potential.
(c) 2006 Microchip Technology Inc.
DS22026A-page 1
MCP1725
Typical Application
MCP1725 Fixed Output Voltage VIN = 2.3V to 2.8V C1 4.7 F 1 2 3 4 On Off PWRGD VIN VIN VOUT 8 Sense 7 VOUT = 1.8V @ 500 mA
SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R1 100 k
C2 1 F
MCP1725 Adjustable Output Voltage VIN = 2.3V to 2.8V C1 4.7 F VOUT = 1.2V @ 500 mA R1 40 k
1 2 3 4
VIN VIN
VOUT 8 ADJ 7
SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R3 100 k R2 20 k
C2 1 F
On Off
PWRGD
DS22026A-page 2
(c) 2006 Microchip Technology Inc.
MCP1725
Functional Block Diagram - Adjustable Output
PMOS VIN VOUT
Undervoltage Lock Out (UVLO)
ISNS
Cf
Rf ADJ
SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA -
Overtemperature Sensing
PWRGD
CDELAY
(c) 2006 Microchip Technology Inc.
DS22026A-page 3
MCP1725
Functional Block Diagram - Fixed Output
PMOS VIN VOUT
Undervoltage Lock Out (UVLO)
ISNS
Cf
Rf Sense
SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA -
Overtemperature Sensing
PWRGD
CDELAY
DS22026A-page 4
(c) 2006 Microchip Technology Inc.
MCP1725
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
VIN ....................................................................................6.5V Maximum Voltage on Any Pin ... (GND - 0.3V) to (VIN + 0.3)V Maximum Power Dissipation......... Internally-Limited (Note 6) Output Short Circuit Duration ................................ Continuous Storage temperature .....................................-65C to +150C Maximum Junction Temperature, TJ ........................... +150C ESD protection on all pins (HBM/MM).............. 2 kV; 200V
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Input Operating Voltage Input Quiescent Current Input Quiescent Current for SHDN Mode Maximum Output Current Line Regulation Load Regulation Output Short Circuit Current Adjust Pin Reference Voltage Adjust Pin Leakage Current Adjust Temperature Coefficient Voltage Regulation Note 1: 2: 3: 4: 5: 6: Sym VIN Iq ISHDN IOUT VOUT/ (VOUT x VIN) VOUT/VOUT IOUT_SC VADJ IADJ TCVOUT VOUT Min 2.3 -- -- 500 -- -1.0 -- 0.402 -10 -- VR - 2.5% 120 0.1 -- 0.05 0.5 1.2 0.410 0.01 40 Typ Max 6.0 220 3 -- 0.16 1.0 -- 0.418 +10 -- Units V A A mA %/V % A V nA ppm/C V Note 1 IL = 0 mA, VIN = Note 1, VOUT = 0.8V to 5.0V SHDN = GND VIN = 2.3V to 6.0V VR = 0.8V to 5.0V, Note 1 (Note 1) VIN 6V IOUT = 1 mA to 500 mA, (Note 4) RLOAD < 0.1, Peak Current VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA VIN = 6.0V, VADJ = 0V to 6V Note 3 Note 2 Conditions
Adjust Pin Characteristics (Adjustable Output Only)
Fixed-Output Characteristics (Fixed Output Only) VR 0.5% VR + 2.5% The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above +150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
7:
(c) 2006 Microchip Technology Inc.
DS22026A-page 5
MCP1725
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Dropout Characteristics Dropout Voltage Power Good Characteristics PWRGD Input Voltage Operating Range VPWRGD_VIN 1.0 1.2 VPWRGD_TH -- 89 90 PWRGD Threshold Hysteresis PWRGD Output Voltage Low PWRGD Leakage PWRGD Time Delay VPWRGD_HYS VPWRGD_L PWRGD_LK TPG 1.0 -- -- -- -- -- 92 92 2.0 0.2 1 6.0 6.0 -- 95 94 3.0 0.4 -- %VOUT V nA IPWRGD SINK = 1.2 mA, ADJ = 0V, SENSE = 0V VPWRGD = VIN = 6.0V Rising Edge RPULLUP = 10 k %VOUT V TA = +25C TA = -40C to +125C For VIN < 2.3V, ISINK = 100 A PWRGD Threshold Voltage (Referenced to VOUT) Falling Edge VOUT < 2.5V Fixed, VOUT = Adj. VOUT >= 2.5V Fixed VIN-VOUT -- 210 350 mV IOUT = 500 mA, (Note 5) VIN(MIN) = 2.3V Sym Min Typ Max Units Conditions
-- 10 -- Detect Threshold to PWRGD Active Time Delay Shutdown Input Logic High Input Logic Low Input SHDN Input Leakage Current Note 1: 2: 3: 4: 5: 6: VSHDN-HIGH VSHDN-LOW SHDNILK 45 -- -0.1 TVDET-PWRGD --
200 30 300 200
-- 55 -- --
s ms ms s
ICDELAY = 140 nA (Typ) CDELAY = OPEN
CDELAY = 0.01 F CDELAY = 0.1 F VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV VIN = 2.3V to 6.0V VIN = 2.3V to 6.0V VIN = 6V, SHDN =VIN, SHDN = GND
-- -- 0.001
-- 15 +0.1
%VIN %VIN A
7:
The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above +150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
DS22026A-page 6
(c) 2006 Microchip Technology Inc.
MCP1725
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters AC Performance Output Delay From SHDN Output Noise TOR eN -- -- 100 2.0 -- -- s V/Hz SHDN = GND to VIN VOUT = GND to 95% VR IOUT = 200 mA, f = 1 kHz, COUT = 10 F (X7R Ceramic), VOUT = 2.5V f = 100 Hz, COUT = 10 F, IOUT = 10 mA, VINAC = 30 mV pk-pk, CIN = 0 F IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V Sym Min Typ Max Units Conditions
Power Supply Ripple Rejection Ratio
PSRR
--
60
--
dB
Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: 5: 6:
TSD TSD
-- --
150 10
-- --
C C
7:
The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above +150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V. Parameters Temperature Ranges Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8LD 2x3 DFN JA -- 52 -- C/W 4-Layer JC51-7 Standard Board with vias 4-Layer JC51-7 Standard Board TJ TJ TA -40 -- -65 -- -- -- +125 +150 +150 C C C Steady State Transient Sym Min Typ Max Units Conditions
Thermal Resistance, 8LD SOIC
JA
--
150
--
C/W
(c) 2006 Microchip Technology Inc.
DS22026A-page 7
MCP1725
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C. Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction Temperature over the Ambient temperature is not significant.
150 Quiescent Current (A) 140 130 120 110 100 90 80 2 3 4 Input Voltage (V) 5 6
0C -45C +25C +90C +130C
IOUT = 0 mA
0.12 Line Regulation (%/V) 0.10
IOUT = 1 mA
VIN = 2.3V to 6.0V IOUT = 500 mA IOUT = 50 mA IOUT = 100 mA IOUT = 250 mA
0.08 0.06 0.04 0.02 0.00 -45 -20 5 30 55 80 105 130 Temperature (C)
FIGURE 2-1: Quiescent Current vs. Input Voltage (1.8V Adjustable).
210 Ground Current (A) 200 190 180 170 160 150 140 130 120 0 100
VIN = 5.0V VIN = 3.3V VIN = 2.5V
FIGURE 2-4: Line Regulation vs. Temperature (1.8V Adjustable).
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00
VOUT = 1.2V Adj
VOUT = 3.3V
Load Regulation (%)
VOUT = 1.8V VOUT = 5V
VOUT = 0.8V
IOUT = 1.0 mA to 500 mA
200
300
400
500
-45
-20
5
30
55
80
105
130
Load Current (mA)
Temperature (C)
FIGURE 2-2: Ground Current vs. Load Current (1.2V Adjustable).
150 Quiescent Current (A) 140 130 120 110 100 90 80 -45 -20 5 30 55 80 105 130 Temperature (C)
VIN = 2.3V VIN = 3.3V VIN = 6.0V VIN = 5.0V
FIGURE 2-5: Load Regulation vs. Temperature (Adjustable Version).
0.412 Adjust Pin Voltage (V) 0.411 0.410 0.409 0.408 -45 -20 5 30 55 80 105 130 Temperature (C)
IOUT = 0 mA
IOUT = 1 mA
VIN = 6.0V VIN = 5.0V
VIN = 2.3V, 3.0V, 4.0V
FIGURE 2-3: Quiescent Current vs. Junction Temperature (1.8V Adjustable).
FIGURE 2-6: Temperature.
Adjust Pin Voltage vs.
DS22026A-page 8
(c) 2006 Microchip Technology Inc.
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C.
0.25 Dropout Voltage (V) 0.20 0.15 0.10 0.05 0.00 0 100 200 300 400 500 Load Current (mA)
150 Quiescent Current (A)
VOUT = 5.0V
140 130 120 110 100 90 80 2
IOUT = 0 mA +130C
VOUT = 2.5V
+90C 0C -45C +25C
3
4 Input Voltage (V)
5
6
FIGURE 2-7: Dropout Voltage vs. Load Current (Adjustable Version).
0.28 Dropout Voltage (V) 0.26 0.24 0.22 0.20 0.18 0.16 -45 -20 5 30 55 80 105 130 Temperature (C)
VOUT = 2.5V VOUT = 5.0V VOUT = 3.3V
FIGURE 2-10: Quiescent Current vs. Input Voltage (0.8V Fixed).
150 Quiescent Current (A) 140 130 120 110 100 90 3 3.5 4 4.5 5 5.5 6 Input Voltage (V)
+135C -45C 0C +25C +90C
IOUT = 500 mA
IOUT = 0 mA
FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version).
35 34 33 32 31 30 29 28 27 26 25
FIGURE 2-11: Quiescent Current vs. Input Voltage (2.5V Fixed).
210 Ground Current (A) 190 170 150 130 110
VOUT = 5.0V VOUT = 2.5V
Power Good Time Delay (ms)
VIN = 2.3V
CDELAY = 0.01 F IOUT = 0 mA
VIN = 5.0V VIN = 3.0V
-45
-20
5
30
55
80
105
130
0
100
200
300
400
500
Temperature (C)
Load Current (mA)
FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature (Adjustable Version).
FIGURE 2-12: Current.
Ground Current vs. Load
(c) 2006 Microchip Technology Inc.
DS22026A-page 9
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C.
140 Quiescent Current (A) 130 120 110 100 90 80 -45 -20 5 30 55 80 105 130 Junction Temperature (C)
VOUT = 0.8V VOUT = 2.5V
IOUT = 0 mA
0.050 Line Regulation (%/V) 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 -45 -20 5 30 55
IOUT = 250 mA IOUT = 1 mA
VOUT = 2.5V VIN = 3.0V to 6.0V
IOUT = 50 mA
IOUT = 500 mA IOUT = 100 mA
80
105
130
Temperature (C)
FIGURE 2-13: Quiescent Current vs. Junction Temperature.
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
FIGURE 2-16: Line Regulation vs. Temperature (2.5V Fixed).
0.20 0.18 Load Regulation (%) 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 -45 -20 5 30 55 80 105 130
VOUT = 0.8V VOUT = 1.2V
VOUT = 0.8V
IOUT = 1.0 mA to 500 mA
ISHDN (A)
VIN = 6.0V VIN = 3.3V
VIN = 2.3V
-45
-20
5
30
55
80
105
130
Temperature (C)
Temperature (C)
FIGURE 2-14:
ISHDN vs. Temperature.
FIGURE 2-17: Load Regulation vs. Temperature (VOUT < 2.5V Fixed).
0.00 Load Regulation (%) -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -45 -20 5 30 55 80 105 130
VOUT = 5.0V IOUT = 1.0 mA to 500 mA VOUT = 2.5V
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -45
Line Regulation (%/V)
IOUT = 1 mA
VIN = 2.3V to 6.0V VOUT = 0.8V
IOUT = 50 mA IOUT = 100 mA IOUT = 250 mA
IOUT = 500 mA
-20
5
30
55
80
105
130
Temperature (C)
Temperature (C)
FIGURE 2-15: Line Regulation vs. Temperature (0.8V Fixed).
FIGURE 2-18: Load Regulation vs. Temperature (VOUT 2.5V Fixed).
DS22026A-page 10
(c) 2006 Microchip Technology Inc.
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C.
0.25
VOUT = 5.0V
10 1 0.1 0.01
VIN = 2.3V VOUT = 0.8V
Dropout Voltage (V)
0.20 0.15 0.10 0.05 0.00 0 100 200 300 400 500 Load Current (mA)
VOUT = 2.5V
VIN = 3.3V VOUT = 2.5V
Noise (V/ Hz)
ILOAD = 200 mA COUT = 1 F CIN = 10 F
0.001 0.01
0.1
1 10 Frequency (kHz)
100
1000
FIGURE 2-19: Current.
0.28 0.26 Dropout Voltage (V) 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 -45 -20 5
VOUT = 2.5V
Dropout Voltage vs. Load
FIGURE 2-22: Output Noise Voltage Density vs. Frequency.
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01
VR=1.2V Adj COUT=4.7 F ceramic X7R VIN=2.5V CIN=0 F IOUT=10 mA
ILOAD = 500 mA VOUT = 5.0V
30
55
80
105
130
0.1
Temperature (C)
1 10 Frequency (kHz)
100
1000
FIGURE 2-20: Temperature.
Dropout Voltage vs.
FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.).
0 -10 PSRR (dB)
1.20 Short Circuit Current (A) 1.10 1.00 0.90 0.80 0.70 0.60 0.50 3.0 3.5
IPEAK VOUT = 2.5V Fixed CIN = 3000 F
-20 -30 -40 -50 -60 -70 -80 0.01
VR=1.2V Adj COUT=22 F ceramic X7R VIN=2.5V CIN=0 F IOUT=10 mA
ISTEADY STATE
4.0
4.5
5.0
5.5
6.0
0.1
Input Voltage (V)
1 10 Frequency (kHz)
100
1000
FIGURE 2-21: Input Voltage.
Short Circuit Current vs.
FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.).
(c) 2006 Microchip Technology Inc.
DS22026A-page 11
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C.
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 0.1
VR=2.5V Fixed COUT=4.7 F ceramic X7R VIN=3.3V CIN=0 F IOUT=10 mA
1 10 Frequency (KHz)
100
1000
FIGURE 2-25: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed).
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 0.1
VR=2.5V Fixed COUT=22 F ceramic X7R VIN=3.3V CIN=0 F IOUT=10 mA
FIGURE 2-28: Shutdown.
2.5V (Adj.) Startup from
1 10 Frequency (KHz)
100
1000
FIGURE 2-26: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed).
FIGURE 2-29: Power Good (PWRGD) Timing with Cdelay of 1000 pF (2.5V Fixed).
FIGURE 2-27:
2.5V (Adj.) Startup from VIN.
FIGURE 2-30: Power Good (PWRGD) Timing with CDELAY of 0.01 F (2.5V Fixed).
DS22026A-page 12
(c) 2006 Microchip Technology Inc.
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 F Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25C.
FIGURE 2-31: (5.0V Fixed).
Dynamic Line Response
FIGURE 2-33: Dynamic Load Response (2.5V Fixed, 1 mA to 500 mA).
FIGURE 2-32: (2.5V Fixed).
Dynamic Line Response
FIGURE 2-34: Dynamic Load Response (2.5V Fixed, 10 mA to 500 mA).
(c) 2006 Microchip Technology Inc.
DS22026A-page 13
MCP1725
3.0 PIN DESCRIPTION
PIN FUNCTION TABLE
Adjustable Output 1 2 3 4 5 6 7
--
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Fixed Output 1 2 3 4 5 6
--
Name VIN VIN SHDN GND PWRGD CDELAY ADJ Sense VOUT EP
Description Input Voltage Supply Input Voltage Supply Shutdown Control Input (active-low) Ground Power Good Output (open-drain) Power Good Delay Set-Point Input Voltage Sense Input (adjustable version) Voltage Sense Input (fixed voltage version) Regulated Output Voltage Exposed Pad of the DFN Package (ground potential)
7 8 Exposed Pad
8 Exposed Pad
3.1
Input Voltage Supply (VIN)
3.4
Power Good Output (PWRGD)
Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 F to 10 F should be sufficient for most applications.
3.2
Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 A.
The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is typically delayed by 200 s (typical, no capacitance on CDELAY pin) from the time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This delay time is controlled by the CDELAY pin.
3.5
Power Good Delay Set-Point Input (CDELAY)
3.3
Ground (GND)
The CDELAY input sets the power-up delay time for the PWRGD output. By connecting an external capacitor from the CDELAY pin to ground, the typical delay times for the PWRGD output can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). This allows for the optimal setting of the system reset time.
Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 120 A), so a heavy trace is not required. For applications have switching or noisy inputs tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients.
DS22026A-page 14
(c) 2006 Microchip Technology Inc.
MCP1725
3.6
3.6.1
Output Voltage Sense/Adjust Input (ADJ/Sense)
ADJ
3.7
Regulated Output Voltage (VOUT)
For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the user the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device.
The VOUT pin(s) is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 F is required for LDO stability. The MCP1725 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 "Output Capacitor" for output capacitor selection guidance.
3.8
Exposed Pad (EP)
3.6.2
Sense
For fixed output voltage versions of the device, the SENSE input is used to provide output voltage feedback to the internal circuitry of the MCP1725. The SENSE pin typically improves load regulation by allowing the device to compensate for voltage drops due to packaging and circuit board layout.
The 2x3 DFN package has an exposed pad on the bottom of the package. This pad should be soldered to the Printed Circuit Board (PCB) to aid in the removal of heat from the package during operation. The exposed pad is at the ground potential of the LDO.
(c) 2006 Microchip Technology Inc.
DS22026A-page 15
MCP1725
4.0 DEVICE OVERVIEW
EQUATION 4-2:
V OUT - V ADJ R 1 = R 2 -------------------------------- V ADJ = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V) The MCP1725 is a high output current, Low Dropout (LDO) voltage regulator with an adjustable delay power-good output and shutdown control input. The low dropout voltage of 210 mV typical at 0.5A of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1725 only draws a maximum of 220 A of quiescent current.
Where: VOUT VADJ
4.1
LDO Output Voltage
4.2
The MCP1725 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for both versions.
Output Current and Current Limiting
4.1.1
ADJUST INPUT
The adjustable version of the MCP1725 uses the ADJ pin (pin 7) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1725. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, the equation for setting VOUT is:
The MCP1725 LDO is tested and ensured to supply a minimum of 0.5A of output current. The MCP1725 has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1725 also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 1.2A (typical). If the overload condition is a soft overload, the MCP1725 will supply higher load currents of up to 1A. The MCP1725 should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 0.5A or less. Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150C, the LDO will shut down the output voltage. See Section 4.9 "Overtemperature Protection" for more information on overtemperature shutdown.
EQUATION 4-1:
R1 + R2 V OUT = V ADJ ------------------ R2 = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V)
Where: VOUT VADJ
4.3
MCP1725-ADJ VIN C1 4.7 F On Off 1 VIN 2 VIN 4 GND
VOUT 8 ADJ 7
Output Capacitor
VOUT R1 C2 1 F
3 SHDN CDELAY 6
PWRGD 5
The MCP1725 requires a minimum output capacitance of 1 F for output voltage stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 F X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1725 to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 F is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature applications of < -25C.
C3 1000 pF
R2
FIGURE 4-1: Typical adjustable output voltage application circuit.
The allowable resistance value range for resistor R2 is from 10 k to 200 k. Solving the equation for R1 yields the following equation:
DS22026A-page 16
(c) 2006 Microchip Technology Inc.
MCP1725
4.4 Input Capacitor
Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 F to 4.7 F is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA (VPWRGD < 0.4V maximum).
VPWRGD_TH VOUT TPG
VOH
TVDET_PWRGD
PWRGD VOL
FIGURE 4-2:
Power Good Timing.
4.5
Power Good Output (PWRGD)
VIN
TOR 70 s
The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section 1.0 "Electrical Characteristics" for Minimum and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in Section 1.0 "Electrical Characteristics"). The power good time delay is adjustable via the CDELAY pin of the LDO (see Section 4.6 "CDELAY Input"). By placing a capacitor from the CDELAY pin to ground, the power good time delay can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3.
30 s SHDN
TPG
VOUT
PWRGD
FIGURE 4-3: Shutdown.
Power Good Timing from
(c) 2006 Microchip Technology Inc.
DS22026A-page 17
MCP1725
4.6 CDELAY Input 4.7 Shutdown Input (SHDN)
The CDELAY input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. By adding a capacitor from the CDELAY pin to ground, the PWRGD power-up time delay can be adjusted from 200 s (no capacitance on CDELAY) to 300 ms (0.1 F of capacitance on CDELAY). See Section 1.0 "Electrical Characteristics" for CDELAY timing tolerances. Once the power good threshold (rising) has been reached, the CDELAY pin charges the external capacitor to VIN. The charging current is 140 nA (typical). The PWRGD output will transition high when the CDELAY pin voltage has charged to 0.42V. If the output falls below the power good threshold limit during the charging time between 0.0V and 0.42V on the CDELAY pin, the CDELAY pin voltage will be pulled to ground, thus resetting the timer. The CDELAY pin will be held low until the output voltage of the LDO has once again risen above the power good rising threshold. A timing diagram showing CDELAY, PWRGD and VOUT is shown in Figure 4-4. The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 s delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30 s delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100 s. See Figure 4-5 for a timing diagram of the SHDN input.
TOR 400 ns (typ) 30 s SHDN 70 s
VOUT
VPWRGD_TH
TPG 0V
CDELAY
VIN (typ)
CDELAY Threshold (0.42V)
PWRGD VOUT
FIGURE 4-4: Diagram.
CDELAY and PWRGD Timing FIGURE 4-5: Diagram. Shutdown Input Timing
DS22026A-page 18
(c) 2006 Microchip Technology Inc.
MCP1725
4.8 Dropout Voltage and Undervoltage Lockout 4.9 Overtemperature Protection
The MCP1725 LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150C. If the LDO junction temperature does reach 150C, the LDO output will be turned off until the junction temperature cools to approximately 140C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 "Application Circuits/Issues" for more information on LDO power dissipation and junction temperature.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.6V differential applied. The MCP1725 LDO has a very low dropout voltage specification of 210 mV (typical) at 0.5A of output current. See Section 1.0 "Electrical Characteristics" for maximum dropout voltage specifications. The MCP1725 LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical). Since the MCP1725 LDO undervoltage lockout activates at 2.04V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.9V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout.
(c) 2006 Microchip Technology Inc.
DS22026A-page 19
MCP1725
5.0
5.1
APPLICATION CIRCUITS/ ISSUES
Typical Application
In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1725 as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation:
The MCP1725 is used for applications that require high LDO output current and a power good output.
MCP1725-2.5
VIN = 3.3V C1 10 F On Off 1 VIN 2 VIN VOUT 8 Sense 7 VOUT = 2.5V @ 0.5A R1 10k
EQUATION 5-2:
P I ( GND ) = V IN ( MAX ) x I VIN Where: PI(GND VIN(MAX) IVIN = = = Power dissipation due to the quiescent current of the LDO Maximum input voltage Current flowing in the VIN pin with no LDO output current (LDO quiescent current)
3 SHDN CDELAY 6 4 GND PWRGD 5
C2 10 F
C3 1000 pF
PWRGD
FIGURE 5-1: 5.1.1
Typical Application Circuit.
APPLICATION CONDITIONS
Package Type = = = = = = = = = 2x3 DFN8 3.3V 5% 3.465V 3.135V 0.350V 2.5V 0.5A maximum 0.4W 30.4C
The total power dissipated within the MCP1725 is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1725 is 120 A. Operating at 3.465V results in a power dissipation of 0.42 milli-Watts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1725 is +125C. To estimate the internal junction temperature of the MCP1725, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RJA) of the device. The thermal resistance from junction to ambient for the 2x3 DFN package is estimated at 76 C/W.
Input Voltage Range VIN maximum VIN minimum VDROPOUT (max) VOUT (typical) IOUT PDISS (typical) Temperature Rise
EQUATION 5-3:
T J ( MAX ) = P TOTAL x R JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature
5.2
5.2.1
Power Calculations
POWER DISSIPATION
The internal power dissipation within the MCP1725 is a function of input voltage, output voltage, output current and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO.
EQUATION 5-1:
P LDO = ( V IN ( MAX ) ) - V OUT ( MIN ) ) x I OUT ( MAX ) ) Where: PLDO VIN(MAX) VOUT(MIN) = = = LDO Pass device internal power dissipation Maximum input voltage LDO minimum output voltage
DS22026A-page 20
(c) 2006 Microchip Technology Inc.
MCP1725
The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation.
5.3
Typical Application
Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected.
EQUATION 5-4:
( T J ( MAX ) - T A ( MAX ) ) P D ( MAX ) = --------------------------------------------------R JA PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature TA(MAX) = maximum ambient temperature RJA = Thermal resistance from junction to ambient
EXAMPLE 5-1:
Package Package Type Input Voltage VIN VOUT IOUT TA(MAX) PLDO(MAX) PLDO PLDO = = = = = = = =
POWER DISSIPATION EXAMPLE
2x3 DFN
3.3V 5% 2.5V 0.5A 60C (VIN(MAX) - VOUT(MIN)) x IOUT(MAX) ((3.3V x 1.05) - (2.5V x 0.975)) x 0.5A 0.51 Watts
LDO Output Voltage and Current
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) x R JA TJ(RISE) = Rise in device junction temperature over the ambient temperature PD(MAX) = Maximum device power dissipation RJA = Thermal resistance from junction to ambient
Maximum Ambient Temperature Internal Power Dissipation
EQUATION 5-6:
T J = T J ( RISE ) + T A TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature
5.3.1
DEVICE JUNCTION TEMPERATURE RISE
The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (RJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 "High Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages". The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application" (DS00792), for more information regarding this subject. TJ(RISE) TJRISE TJRISE = = = PTOTAL x RJA 0.51 W x 76.0 C/W 38.8C
(c) 2006 Microchip Technology Inc.
DS22026A-page 21
MCP1725
5.3.2 JUNCTION TEMPERATURE ESTIMATE
5.4
CDELAY Calculations (typical)
T C = I * -----V
To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 38.8C + 60.0C TJ = 98.8C As you can see from the result, this application will be operating near around a junction temperature of 100C. The PCB layout for this application is very important as it has a significant impact on the junctionto-ambient thermal resistance (RJA) of the 2x3 DFN package, which is very important in this application.
Where: C I T V = = = = CDELAY Capacitor CDELAY charging current, 140 nA typical. time delay CDELAY threshold voltage, 0.42V typical
- 09 T ( 140nA * T ) C = I * ------ = --------------------------------- = 333.3 x10 * T V 0.42V
For a delay of 300ms, C = 333.3E-09 *.300 C = 100E-09 F (0.1 F)
5.3.3
MAXIMUM PACKAGE POWER DISSIPATION AT 60C AMBIENT TEMPERATURE
PD(MAX) PD(MAX) PD(MAX) PD(MAX) = = = = (125C - 60C) / 76 C/W 0.855W (125C - 60C)/ 163 C/W 0.399W
2x3 DFN (76 C/W RJA):
SOIC8 (163C/Watt RJA):
From this table, you can see the difference in maximum allowable power dissipation between the 2x3 DFN package and the 8-pin SOIC package. This difference is due to the exposed metal tab on the bottom of the DFN package. The exposed tab of the DFN package provides a very good thermal path from the die of the LDO to the PCB. The PCB then acts like a heatsink, providing more area to distribute the heat generated by the LDO.
DS22026A-page 22
(c) 2006 Microchip Technology Inc.
MCP1725
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (2x3) XXXX XYWW NN Standard Extended Temp Code Voltage Options * Code Voltage Options * Example: ABL 649 25
ABL 0.8 ABR 3.0 ABM 1.2 ABS 3.3 ABP 1.8 ABT 5.0 ABQ 2.5 ABU ADJ * Custom output voltages available upon request. Contact your local Microchip sales office for more information. 8-Lead SOIC (150 mil) Example:
XXXXXXXX XXXXYYWW NNN
250802E e3 SN^^0649 256
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2006 Microchip Technology Inc.
DS22026A-page 23
MCP1725
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3 Body (DFN) - Saw Singulated
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D b N L
e N
K E E2
EXPOSED PAD NOTE 1 1 2 D2 2 1 NOTE 1
TOP VIEW
BOTTOM VIEW
A
A3
A1
NOTE 2 MILLIMETERS NOM 8 0.50 BSC 0.90 0.02 0.20 REF 2.00 BSC 3.00 BSC -- -- 0.25 0.40 --
Units Dimension Limits Number of Pins N Pitch e Overall Height A Standoff A1 Contact Thickness A3 Overall Length D Overall Width E Exposed Pad Length D2 Exposed Pad Width E2 Contact Width b Contact Length L Contact-to-Exposed Pad K
MIN
MAX
0.80 0.00
1.00 0.05
1.30 1.50 0.18 0.30 0.20
1.75 1.90 0.30 0.50 --
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-123, Sept. 8, 2006
DS22026A-page 24
(c) 2006 Microchip Technology Inc.
MCP1725
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
E E1
p D 2 B n 1
h 45
c A
A2
L A1
MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness .052 .061 1.55 A2 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .146 .157 3.99 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
Units Dimension Limits n p
MIN
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
(c) 2006 Microchip Technology Inc.
DS22026A-page 25
MCP1725
NOTES:
DS22026A-page 26
(c) 2006 Microchip Technology Inc.
MCP1725
APPENDIX A: REVISION HISTORY
Revision A (December 2006)
* Original Release of this Document.
(c) 2006 Microchip Technology Inc.
DS22026A-page 27
MCP1725
NOTES:
DS22026A-page 28
(c) 2006 Microchip Technology Inc.
MCP1725
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX X X X/ XX Examples:
a) MCP1725-0802E/MC: 0.8V Low Dropout Regulator, 8LD DFN pkg.
Output Feature Tolerance Temp. Package Voltage Code
b)
Device: MCP1725: 500 mA Low Dropout Regulator MCP1725T: 500 mA Low Dropout Regulator Tape and Reel
MCP1725T-1202E/MC: Tape and Reel, 1.2V Low Dropout Regulator, 8LD DFN pkg. MCP1725-1802E/MC: 1.8V Low Dropout Voltage Regulator, 8LD DFN pkg.
c)
Output Voltage *: 08 12 18 25 30 33 50 0 2 E = = = = = = = 0.8V "Standard" 1.2V "Standard" 1.8V "Standard" 2.5V "Standard" 3.0V "Standard" 3.3V "Standard" 5.0V "Standard"
d)
MCP1725T-2502E/MC: Tape and Reel, 2.5V Low Dropout Voltage Regulator, 8LD DFN pkg. MCP1725-3002E/MC: 3.0V Low Dropout Voltage Regulator, 8LD DFN pkg. 3.3V Low Dropout Voltage Regulator, 8LD DFN pkg.
*Contact factory for other output voltage options Extra Feature Code: Tolerance: Temperature: Package Type: = Fixed
e)
f)
= 2.0% (Standard) = -40C to +125C
MCP1725-3302E/MC:
g)
MC = Plastic Dual Flat No Lead (DFN) (2x3 Body), 8-lead SN = Plastic Small Outline (150 mil Body), 8-lead
MCP1725T-5002E/MC: Tape and Reel, 5.0V Low Dropout Voltage Regulator, 8LD DFN pkg. MCP1725-ADJE/MC: ADJ Low Dropout Voltage Regulator, 8LD DFN pkg.
h)
i)
MCP1725T-0802E/SN: Tape and Reel, 0.8V Low Dropout Voltage Regulator, 8LD SOIC pkg. MCP1725-1202E/SN: 1.2V Low Dropout Voltage Regulator, 8LD SOIC pkg.
j)
k)
MCP1725T-1802E/SN: Tape and Reel, 1.8V Low Dropout Voltage Regulator, 8LD SOIC pkg. MCP1725-2502E/SN: 2.5V Low Dropout Voltage Regulator, 8LD SOIC pkg. 3.0V Low Dropout Voltage Regulator, 8LD SOIC pkg. 3.3V Low Dropout Voltage Regulator, 8LD SOIC pkg.
l)
m)
MCP1725-3002E/SN:
n)
MCP1725-3302E/SN:
o)
MCP1725T-5002E/SN: Tape and Reel, 5.0V Low Dropout Voltage Regulator, 8LD SOIC pkg. MCP1725T-ADJE/SN: Tape and Reel, ADJ Low Dropout Voltage Regulator, 8LD SOIC pkg.
p)
(c) 2006 Microchip Technology Inc.
DS22026A-page 29
MCP1725
NOTES:
DS22026A-page 30
(c) 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2006 Microchip Technology Inc.
DS22026A-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS22026A-page 32
(c) 2006 Microchip Technology Inc.

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